The present invention relates to a semiconductor integrated circuit memory, and more particularly to a semiconductor integrated circuit memory made of GaAs which is a compound semiconductor. In more detail, the present invention relates to a semiconductor LSI memory (namely, a semiconductor large scale integration circuit memory) which includes very fine memory cells and is excellent in alpha-particle immunity.
In the past, little attention has been paid to the alpha-particle immunity of a GaAs LSI. For example, as described in the IEEE, International Solid-State Circuits Conference Digest of Technical Papers Volume XXX, 1987, pages 140 and 141, MESFET's (hereinafter referred to as "FET's") and other circuit elements are formed directly a semi-insulating GaAs substrate, and the alpha-particle immunity of the GaAs LSI and the counterplan thereto are not considered.
However, as described in the IEEE, Electron Device Letter, Vol. EDL-7, No.6, June 1986, pages 396 and 397, when an FET formed on a GaAs substrate is irradiated with alpha-particles, an electric charge of about 800 fc is generated in the FET, and this value is several times greater than a value expected from the energy of the alpha-particles. Further, when a P-type layer opposite in conductivity type to an N-channel of the FET is formed beneath the bottom of the FET, the charge generated in the FET is reduced to about 100 fc which is a fraction of the above value. An example of a GaAs LSI which includes a P-buried layer, is described on pages 138 and 139 of the above-referred IEEE International Solid-State Circuits Conference Digest of Technical Papers, 1978. In this example, the P-buried layer is formed all over a GaAs LSI under the same manufacturing conditions, and the dosage in forming the P-buried layer through ion implantation techniques is as high as about 2.times.10.sup.12 cm.sup.-2.
Unfortunately, if it is intended to improve the alpha-particle immunity of an LSI memory including a very small memory cell made by employing this example, the operation speed of the LSI memory will be reduced. This is the case since it requires an increase in the amount of the ion implanting dosage into the P-type layer which changes the P-type layer from being a depleted layer to a conductive layer and produces parasitic capacitance.